1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a cell that supplies a prescribed voltage to a well of a memory cell of an SRAM (Static Random Access Memory).
2. Description of the Background Art
In recent years, with widespread use of mobile terminal equipment, digital signal processing in which bulk data such as sounds or images is processed at high speed has been increasingly important. SRAM which is capable of high-speed access processing holds an important place as a semiconductor memory device to be mounted on such mobile terminal equipment.
SRAM has a memory cell configured with a P-channel MOS transistor and an N-channel MOS transistor which are formed in an N well region and a P well region, respectively.
FIG. 16 schematically shows a general memory array.
Referring to FIG. 16, the memory array has memory cells MC integrated and arranged in a matrix.
Power feed to the N well region and the P well region of memory cell MC (well feed) may be performed for each memory cell. In the case where power is fed individually for each memory cell, however, a region for interconnection for well feed has to be reserved for each and therefore an individual area of a memory cell MC is increased. Accordingly, the area of the entire memory array is increased.
Therefore, usually, well feed is performed on the basis of a plurality of cells rather than being performed individually for each memory cell.
Here, as an example, a cell PMC for executing well feed every four memory cells (also simply referred to as a power feed cell hereinafter) is provided on each column along the Y direction. A plurality of power feed cells are provided along the X direction to configure a power feed cell row. FIG. 16 shows two power feed cell rows each comprised of a plurality of power feed cells.
FIG. 17 is a circuit configuration diagram of a memory cell MC.
Referring to FIG. 17, memory cell MC includes transistors PT1, PT2, NT1-NT4. Here, transistors PT1, PT2 are P-channel MOS transistors, by way of example, and transistors NT1-NT4 are N-channel MOS transistors, by way of example.
Here, transistors NT3, NT4 are a pair of access transistors provided between a storage node and a bit line BL and a complementary bit line /BL paired with bit line BL, respectively. Transistors PT1, PT2 are a pair of load transistors each provided between a storage node and a high-side power supply voltage. Transistors NT1, NT2 are a pair of driver transistors each provided between a storage node and a low-side power supply voltage. These load transistors and driver transistor form two inverters in memory cell MC.
Specifically, transistor PT1 is arranged between a high-side power supply voltage ARVDD (also referred to as voltage ARVDD hereinafter) and a storage node Nd1 and has the gate electrically coupled to a storage node Nd2. Transistor NT1 is arranged between storage node Nd1 and a low-side power supply voltage ARVSS (also referred to as voltage VSS hereinafter) and has the gate electrically coupled to storage node Nd2. Transistor PT2 is arranged between voltage ARVDD and storage node Nd2 and has the gate electrically coupled to storage node Nd1. Transistor NT2 is arranged between storage node Nd2 and voltage ARVSS and has the gate electrically coupled to storage node Nd1.
Transistors PT1, PT2 and NT1, NT2 form two CMOS inverters for holding signal levels at storage nodes N1 and N2, which are cross-coupled to configure a CMOS-type flip-flop.
Transistor NT3 is arranged between storage node Nd1 and bit line BL and has the gate electrically coupled to a word line WL. Transistor NT4 is arranged between storage node Nd2 and bit line /BL and has the gate electrically coupled to word line WL.
Data writing/reading for storage nodes Nd1 and Nd2 are executed by transistors NT3 and NT4 turning on in response to activation of word line WL to allow storage nodes Nd1 and Nd2 to be electrically coupled to bit lines BL and /BL, respectively.
For example, when word line WL is inactivated to turn off transistors NT3, NT4, one of the N-channel MOS transistor and the P-channel MOS transistor which configure each CMOS inverter turns on, according to the data level held at storage nodes Nd1 and Nd2. Accordingly, according to the data level held in memory cell MC, storage nodes Nd1 and Nd2 are electrically coupled to one and the other of the high-side power supply voltage corresponding to an “H” level of data and the low-side power supply voltage corresponding to an “L” level of data.
Then, it becomes possible to hold data in memory cell MC in the standby state in which word line WL is inactivated.
Furthermore, in this configuration, a high-side power supply voltage VDDB (also referred to as N well voltage VDDB hereinafter) is supplied to the back gates, namely the N well regions of transistors PT1, PT2 which are P-channel MOS transistors, and a low-side power supply voltage VSSB (also referred to as P well voltage VSSB) is supplied to the back gates, namely the P well regions of transistors NT1-NT4 which are N-channel MOS transistors. In other words, N well voltage VDDB is supplied to the N well region forming a P-channel MOS transistor of memory cell MC, and P well voltage VSSB is supplied to the P well region forming an N-channel MOS transistor.
In particular, in this configuration, high-side power supply voltages ARVDD and VDDB as well as low-side power supply voltages ARVSS and VSSB can independently be supplied. In other words, voltages ARVDD, ARVSS for driving memory cell MC and N well voltages VDDB, VSSB for well feed are independently supplied, so that the well voltage is enhanced thereby improving software error resistance.
FIG. 18 illustrates a layout pattern of memory cells and power feed cells of a conventional memory array.
Referring to FIG. 18, here, power feed cell PMCP is provided between two memory cells MC, and four memory cells MC and two power feed cells PMCP are shown. Furthermore, a P well region and an N well region in which active regions for forming memory cell MC and power feed cell PMCP are disposed are alternately disposed in the row direction, namely in the X direction to extend in the column direction, namely in the Y direction.
The layout of memory cell MC and power feed cell PMCP which is reflective-symmetric with respect to a boundary region is repeatedly arranged, and memory cell MC and power feed cell PMCP have active regions and interconnection lines disposed in reflective symmetry in the Y direction. Here, although not shown, in a memory cell column, active regions and interconnection lines are disposed in reflective symmetry in the X direction between adjacent memory cells MC.
Although memory cell MC and power feed cell PMCP are different in interconnection and the like, an active region and an interconnection line are disposed in power feed cell PMCP using a similar layout pattern as memory cell MC in order to make the layout patterns uniform. In other words, in the column direction, power feed cell PMCP is formed using a dummy layout pattern similar to the layout pattern of memory cell MC to have a reflective-symmetric relation in the X direction with the adjacent memory cell MC.
The use of this layout pattern makes it possible to shape uniform layout patterns having reduced pattern variations with the continuity of layout patterns of the cell layout being kept.
FIG. 19 illustrates a part of the cell layout shown in FIG. 18.
Referring to FIG. 19, shown here are two memory cells MC and a power feed cell PMCP arranged therebetween in a memory cell column.
In the following, a layout pattern of memory cell MC and power feed cell PMCP will be described.
FIG. 20 illustrates a layout pattern of memory cell MC.
FIG. 20(a) shows a layout pattern of an underlying portion of memory cell MC.
Referring to FIG. 20(a), an N-type N well region is disposed to extend linearly in the Y direction, and P-type P well regions are disposed on opposite sides of the N well region. A load transistor is formed in the N well region, and an access transistor and a driver transistor are provided in the P well region. These N well region and P well regions are arranged to extend in the column direction, and memory cells MC aligned in a line are formed using these N well region and P well regions.
Specifically, in the P well region, a rectangular-shaped, transistor formation active region (also simply referred to as an active region hereinafter) 100 is formed to extend in the Y direction. A polysilicon interconnection line 105 and a polysilicon interconnection line 104 for forming a storage node are disposed in the X direction each to intersect active region 100. Polysilicon interconnection line 105 is disposed to extend into the N well region. Polysilicon interconnection line 104 is disposed in the P well region.
A contact 110 for forming a storage node is disposed between polysilicon interconnection lines 104 and 105. A contact 111 for establishing contact with bit line BL as described later is disposed in an outer region of active region 100 which is divided by polysilicon interconnection line 105. In addition, a contact 109 for establishing contact with an interconnection line receiving voltage ARVSS as described later is disposed in an outer region of active region 100 which is divided by polysilicon interconnection line 104.
Furthermore, a contact 108 for forming a gate region and establishing contact with word line WL as describe later is disposed above polysilicon interconnection line 104.
In the N well region, rectangular-shaped active regions 102, 103 extending in the Y direction are arranged spaced apart from each other and displaced from each other in the Y direction. Polysilicon interconnection line 105 is disposed to extend in the X direction across active region 102. A polysilicon interconnection line 107 is disposed to extend in the X direction across active region 103 as well. A contact 112 for establishing contact with an interconnection line receiving voltage ARVDD is disposed in an outer region of active region 102 which is divided by polysilicon interconnection line 105. Furthermore, a contact 115 for establishing contact with an interconnection line receiving voltage ARVDD is disposed in an outer region of active region 103 which is divided by polysilicon interconnection line 107.
In active region 102, a shared-contact 113 is formed which establishes contact with polysilicon interconnection line 107 in common with the active region gate-isolated by polysilicon interconnection line 105. In active region 103, a shared contact 114 is formed which establishes contact with polysilicon interconnection line 105 in common with the active region gate-isolated by polysilicon interconnection line 107. Formation of this shared contact 113 allows electrical connection to both active region 102 and polysilicon interconnection line 107 with one contact without using one-layer metal. Furthermore, formation of shared contact 114 allows electrical connection to both active region 103 and polysilicon interconnection line 105 with one contact without using one-layer metal.
In the other P well region, a rectangular-shaped active region 101 is formed to extend in the Y direction. A polysilicon interconnection line 106 and polysilicon interconnection line 107 provided extending from the N well region are disposed in the X direction, each intersecting active region 101. Polysilicon interconnection line 106 is disposed in the P well region.
A contact 117 for forming the other storage node is disposed between polysilicon interconnection lines 106 and 107. A contact 116 for establishing contact with the complementary bit line /BL as described later is disposed in an outer region of active region 101 which is divided by polysilicon interconnection line 107. Furthermore, a contact 118 for establishing contact with an interconnection line receiving voltage ARVSS as described later is disposed in an outer region of active region 101 which is divided by polysilicon interconnection line 106. In addition, a contact 119 for forming a gate region and establishing contact with word line WL as described later is disposed above polysilicon interconnection line 106.
The positional relation between the contacts for bit lines BL, /BL and the contacts receiving voltage ARVSS is symmetric between active regions 100 and 101.
Here, the region surrounded by the dotted line as shown is a region in which P-type ion implantation is performed on active regions 102, 103 of N well regions in order to form impurity regions of P-channel MOS transistors. A region not surrounded by a dotted line is subjected to N-type ion implantation.
FIG. 20(b) shows a layout pattern up to a first metal interconnection layer (also referred to as the first layer) of memory cell MC.
As shown in FIG. 20(b), in the first layer, a metal 123 is provided electrically connected to contact 108. Furthermore, a metal 122 is provided electrically connected to contact 111. In addition, a metal 128 is provided electrically coupling contact 110 forming a storage node and shared contact 113 to each other. A metal 127 is provided electrically connected to contact 112. A metal 129 is provided electrically coupling contact 117 forming a storage node and shared contact 114 to each other. Additionally provided are a metal 126 electrically connected to contact 118, a metal 120 connected to contact 119, and a metal 121 connected to contact 116.
FIG. 20(c) shows a layout pattern up to a second metal interconnection layer (also referred to as the second layer) of memory cell MC.
As shown in FIG. 20(c), in the second layer, a metal 131 is provided electrically coupled to metal 122 through a contact 130. Furthermore, a metal 133 is provided electrically coupled to metal 123 through a contact 132. In addition, a metal 135 is provided electrically coupled to metal 124 through a contact 134. Furthermore, a shared metal 137 is provided electrically coupled to metals 127 and 125 through contacts 136 and 138, respectively. Moreover, a metal 140 is provided electrically coupled to metal 126 through a contact 139. In addition, a metal 141 is provided electrically coupled to metal 120 through a contact 142. In addition, a metal 144 is provided electrically coupled to metal 121 through a contact 143.
Here, metal 135 and metal 140 form bit lines BL and /BL, respectively. Metal 137 forms a power supply line which supplies voltage ARVDD.
FIG. 20(d) shows a layout pattern up to a third metal interconnection layer (also referred to as the third layer) of memory cell MC.
As shown in FIG. 20(d), in the third layer, a metal 151 is provided electrically coupled to metal 131 through a contact 150. Furthermore, a metal 154 is provided electrically coupled to metal 133 through a contact 152 and coupled to metal 141 through a contact 153. In addition, a metal 156 is provided electrically coupled to metal 144 through a contact 155.
Here, metal 151 forms a power supply line supplying voltage ARVSS. Metal 154 forms word line WL. Furthermore, metal 156 forms a power supply line supplying voltage ARVSS.
In other words, power supply lines and bit lines BL, /BL and word line WL are formed using the second and third metal interconnection layers.
FIG. 21 illustrates a layout pattern of a conventional power feed cell PMCP.
FIG. 21(a) shows a layout pattern of an underlying portion of power feed cell PMCP.
Referring to FIG. 21(a), an N-type N well region is disposed to linearly extend in the Y direction, and P-type P well regions are disposed on opposite sides of the N well region. These N well region and P well regions are shared with memory cell MC and arranged extending in the column direction. In these N well region and P well regions, a power feed cell for performing well feed is formed using transistor formation active regions formed as a dummy layout pattern.
Specifically, in the middle region of the P well region of the power feed cell, a dummy active region 207 for feeding a well voltage is disposed. Furthermore, a dummy active region 208 for feeding a well voltage is disposed similarly in the middle portion of the other P well region. In addition, a dummy active region 204 for feeding a well voltage is disposed in the middle portion of the N well region.
Then, in the upper region, in a boundary region between the upper, adjacent memory cell MC and power feed cell which constitute the same column, the aforementioned active region 100 of memory cell MC in the column direction is shown. As described above, the layout patterns of memory cells MC adjacent in the memory cell column are formed in reflective symmetry along the X direction, and active region 100 is disposed to extend along the Y-axis direction. Here, to form a power feed cell, active region 100 is configured to be disposed not extending in the power feed cell. Similarly, active regions 103 and 101 are also configured to be disposed not extending in the power feed cell.
Similarly, in the lower region, in a boundary region between the lower, adjacent memory cell MC and the power feed cell which constitute the same column on the lower side, an active region 200 for forming the lower adjacent memory cell MC is shown. As described above, to form a power feed cell, active region 200 is configured to be disposed not extending in the power feed cell. Similarly, active regions 203, 201 are also configured to be disposed not extending in the power feed cell.
Then, a dummy polysilicon interconnection line is disposed in order to keep the continuity of the layout pattern. Specifically, dummy polysilicon interconnection lines 222-225 are provided along the X direction in reflective symmetry with the layout pattern of the adjacent memory cell MC. In the upper region, polysilicon interconnection line 225 is disposed along the X direction in an end region of active region 100, and polysilicon interconnection line 224 is disposed to extend along the X direction in end regions of active regions 103 and 101. On the other hand, in the lower region, polysilicon interconnection line 223 is disposed to extend along the X direction in an end region of active region 201, and polysilicon interconnection line 222 is disposed to extend along the X direction in end regions of active regions 200, 203.
Then, contacts electrically coupled to polysilicon interconnection lines 222-225 are disposed to keep continuity of the layout pattern.
Specifically, a shared contact 219 is disposed which establishes a shared contact for polysilicon interconnection line 222 and dummy active region 204. A contact 217 is disposed for polysilicon interconnection line 223. Furthermore, a shared contact 216 is disposed which establishes a shared contact for polysilicon interconnection line 224 and dummy active region 204. A contact 213 is disposed for polysilicon interconnection line 225.
Then, in dummy active region 207, a contact 209 is disposed for establishing contact with a power supply line supplying P well voltage VSSB to be fed to the P well. In dummy active region 204, a contact 210 is disposed for establishing contact with a power supply line supplying N well voltage VDDB to be fed to the N well. In dummy active region 208, a contact 211 is disposed for establishing contact with a power supply line supplying P well voltage VSSB to be fed to the P well.
Here, the region surrounded with the dotted line as shown is a region in which P-type ion implantation is performed on active regions 207, 208 in the P well regions. It is noted that the region not surrounded with a dotted line is a region subjected to N-type ion implantation.
FIG. 21(b) shows a layout pattern up to the first metal interconnection layer of power feed cell PMCP.
As shown in FIG. 21(b), in the first layer, a metal 236 is provided which is electrically connected to contact 213 and contact 209. In addition, a metal 235 is provided which is electrically connected to shared contacts 216, 219 and contact 210. In addition, a metal 231 is provided which is electrically connected to contact 211 and contact 217.
In the upper region, in the boundary region between the upper adjacent memory cell MC and the power feed cell which constitute the same column, the metals having the aforementioned active regions 100, 101, 103 of memory cell MC in the column direction connected through the contacts are denoted by the same reference characters and are similar to those illustrated in FIG. 20(b). Therefore, a detailed description thereof will not be repeated.
Similarly, in the lower region, in the boundary region between the lower adjacent memory cell MC and the power feed cell which constitute the same column on the lower side, active region 200 for forming the lower adjacent memory cell MC is shown and is electrically coupled to a metal 234 through a contact 221. Active region 203 is electrically coupled to a metal 233 through a contact 220. Active region 201 is electrically coupled to a metal 232 through a contact 218.
FIG. 21(c) shows a layout pattern up to the second metal interconnection layer of power feed cell PMCP.
As shown in FIG. 21(c), in the second layer, a metal 255 is provided which is electrically coupled to metal 235 through a contact 254. Furthermore, a metal 253 is provided which is electrically coupled to metal 236 through a contact 252. In addition, a metal 243 is provided which is electrically coupled to metal 231 through a contact 242. Moreover, a metal 245 is provided which is electrically coupled to metal 231 through a contact 244. This metal 245 is a dummy metal formed in accordance with the same layout pattern as metals 253, 255, 243.
As for the upper region, in the boundary region between the upper adjacent memory cell MC and the power feed cell which constitute the same column, metal 135 forming bit line BL electrically coupled through contact 134 of memory cell MC as illustrated in FIG. 20(c) is disposed to extend along the Y direction. Furthermore, metal 137 forming a power supply line supplying voltage ARVDD electrically coupled through contact 138 of memory cell MC is disposed to extend along the Y direction. Similarly, metal 140 forming bit line /BL of memory cell MC is disposed to extend along the Y direction.
Similarly, in the lower region, in the boundary region between the lower adjacent memory cell MC and the power feed cell which constitute the same column on the lower side, metal 234 and a metal 257 are electrically coupled to each other through a contact 256. Furthermore, metal 233 and metal 137 are electrically coupled to each other through a contact 249. In addition, metal 232 and metal 140 are electrically coupled to each other through a contact 246.
FIG. 21(d) shows a layout pattern up to the third metal interconnection layer of power feed cell PMCP.
As shown in FIG. 21(d), in the third layer, a shared metal 263 is provided which is electrically coupled to metal 253 and metal 243 through contacts 268 and 262, respectively. Furthermore, a metal 265 is provided which is electrically couple to metal 255 through a contact 264. It is noted that metal 245 is provided as a dummy metal as described above and is not electrically coupled to metal 245 and metal 265 through a contact.
This metal 263 forms a power supply line supplying P well voltage VSSB, and metal 265 forms a power supply line supplying N well voltage VDDB.
As for the upper region, in the boundary region between the upper adjacent memory cell MC and the power feed cell which constitute the same column, metal 156 forming the power supply line electrically coupled through contact 155 of memory cell MC as illustrated in FIG. 20(d) is disposed to extend along the X direction.
On the other hand, as for the lower region, in the boundary region between the lower adjacent memory cell MC and the power feed cell which constitute the same column on the lower side, metal 257 is electrically coupled to a metal 267 through a contact 266. This metal 267 is formed as a power supply line supplying voltage ARVSS provided for the lower adjacent memory cell MC.
In other words, in this configuration, as for N well voltage VDDB, the well voltage is supplied through a path of metal 265-contact 264-metal 255-contact 254-metal 235-contacts 216, 219, 210-dummy active region 204. On the other hand, as for P well voltage VSSB, the well voltage is supplied through a path of metal 263-contacts 262, 268-metals 253, 243-contacts 252, 242-metals 236, 231-contacts 209, 211-dummy active regions 207, 208.
FIG. 22 is a structural view in cross section along II-II of power feed cell PMCP.
Referring to FIG. 22, metal 263 supplying P well voltage VSSB is provided in the third layer. Metals 135, 140 forming bit lines BL, /BL and metal 137 supplying voltage ARVDD are provided in the second layer as described above. Metal 235 electrically coupled to N well voltage VDDB is provided in the first layer and is electrically coupled to active region 204 subjected to N+ ion implantation in the N well region through contact 210.
Metal 236 electrically coupled to P well voltage VSSB is electrically coupled to active region 207 subjected to P+ ion implantation in the P well region through contact 209. Metal 231 electrically coupled to P well voltage VSSB is electrically coupled to active region 208 subjected to P+ ion implantation in the P well region through contact 211.
The configuration in power feed cell PMCP allows N well voltage VDDB to be supplied to the N well region through dummy active region 204 and allows P well voltage VSSB to be supplied to the P well regions through dummy active regions 207 and 208.
Accordingly, well feed can be performed on the basis of a plurality of cells so that the layout area of each memory cell MC is reduced thereby reducing the layout area of the memory array as a whole.
On the other hand, the conventional power feed cell has the following problems in its layout.
FIG. 23 is a layout diagram in a case where a power supply line is disposed for the conventional power feed cell.
Here, a part of the metals illustrated in FIGS. 21(c) and (d) is shown.
In the memory array, four interconnection tracks are provided along the Y direction. Specifically, interconnection tracks 2M0-2M3 provided here in the second metal interconnection layer are shown along the Y direction. Three of them are used as bit lines BL, /BL and a power supply line supplying voltage ARVDD. Here, 3M0, 3M1 represent interconnection tracks provided in the third metal interconnection layer to form power supply lines supplying P well voltages VSSB and VDDB.
Therefore, in order to provide interconnection along the Y direction so as not to interfere with these bit lines BL, /BL and the power supply line for voltage ARVDD, the region corresponding to the remaining one interconnection track is used to interconnect metals for establishing contact between the power supply lines (N well voltages VDDB, VSSB) provided in the third metal interconnection layer along the X direction and the active region in the underlying region. In other words, a piling region from the third metal interconnection layer to the underlayer has to be secured. The piling region refers to an interconnection space required to establish contact with an underlying metal interconnection layer. Here, by way of example, the aforementioned metals 253, 255 each of 0.1 μm in the X direction and 0.5 μm in the Y direction are aligned in the Y direction.
This piling region needs to be provided for each of the power supply line supplying N well voltage VDDB and the power supply line supplying P well voltage VSSB, so that some area needs to be secured to some extent. Therefore, the area of power feed cell PMCP cannot be reduced in order to secure these two piling regions. In other words, the layout area of the power feed cell is inevitably increased by the lengths of the metals in the Y direction to be used for interconnection from two power supply lines formed in the same metal interconnection layer to the underlayer.